Loopback tests are often used to confirm operability of transmit and receive circuits within signal transceivers. In a typical test arrangement, a pseudorandom bit sequence (PRBS) generator delivers a sequence of test data values to the transmit circuit which outputs a corresponding test signal onto a signal path. The signal path is looped-back to the input of the receive circuit which responds to the incoming test signal by generating a sequence of received data values that corresponds to the original test data sequence. The test data sequence and received data sequence are compared bit-for-bit to confirm error-free signal transmission and reception, with an error being signaled in the event of a mismatch.
While conventional loopback testing is usually sufficient for testing transceiver circuits themselves, higher level logic circuits which operate in response to specific incoming data sequences or control codes are often excluded from the loopback test path, and therefore either remain untested or require additional logic-level test circuitry to carry out further test operations.